Adaptive Cancellation of Voltage Offset in a Communication System

ABSTRACT

Described embodiments include a receiver for a serial-deserializer or the like. The receiver has adaptive offset voltage compensation capability. The offset voltage is canceled by a controller in a feedback loop to generate a compensation signal depending on a data decision error signal or by timing signals used for clock recovery.

CROSS-REFERENCE TO RELATED APPLICATIONS

The subject matter of this application is related to U.S. patentapplication Ser. No. 13/231,097 filed on Sep. 13, 2011 and Ser. No.13/315,831 filed on Dec. 9, 2011, the teachings of which areincorporated herein in their entireties by reference.

BACKGROUND

In many data communication applications, serializer and de-serializer(SERDES) devices facilitate the transmission of parallel data betweentwo points across a serial link. Data at one point is converted fromparallel data to serial data and transmitted through a communicationschannel to the second point where it received and converted from serialdata to parallel data.

At high data rates frequency-dependent signal loss from thecommunications channel (the signal path between the two end points of aserial link), as well as signal dispersion and distortion, can occur.Ideally, without noise, jitter, and other loss and dispersion effects, adata eye at the receiver will exhibit a relatively ideal shape. Inpractice, the shape of the data eye changes with noise, jitter, otherloss and dispersion effects, and with temperature and voltagevariations. As such, the communications channel, whether wired, optical,or wireless, acts as a filter and might be modeled in the frequencydomain with a transfer function. Correction for frequency dependentlosses of the communications channel, and other forms of signaldegradation, often requires signal equalization of the signal at areceiver.

Equalization through use of one or more equalizers compensates for thesignal degradation to improve communication quality. Equalization mightalso be employed at the transmit side to pre-condition the signal.Equalization, a form of filtering, generally requires some estimate ofthe transfer function of the channel to set its filter parameters.However, in many cases, the specific frequency-dependent signaldegradation characteristics of a communications channel are unknown, andoften vary with time. In such eases, an equalizer with adaptive settingof parameters providing sufficient adjustable range might be employed tomitigate the signal degradation of the signal transmitted through thecommunications channel. Equalization might be through a front-endequalizer, a feedback equalizer, or some combination of both. The shapeof the data eye also changes due to equalization applied to input signalof the receiver. In some systems, equalization applied by atransmitter's equalizer further alters the shape of the eye from theideal.

If an analog front-end equalizer (AFE) is employed, the dataeye-operating margin improves. However, better performance might beachieved through use of at least one of a Decision Feedback Equalizer(DFE) and a feed forward equalizer (FFE) in combination with an AFE. TheDFE might be employed to optimize for post-cursor intersymbolinterference (ISO) and the FFE might be employed to reduce precursorISI. Use of a DEE and/or an FFE might open the vertical and horizontaldata eye opening.

Differential signaling is widely used signaling in SERDES systems. Indifferential signaling, two complimentary signals are sent on twoseparate wires and the difference between the two signals is determinedat the receiver. In an ideal situation, the circuitry handling the twocomplimentary signals are perfectly matched to avoid introducing anadditional, or offset, voltage between the differential signals. Inreality, however, there is typically a mismatch between the devices usedin the circuitry and the AFE circuits themselves typically introduce anunknown and relatively slowly varying offset voltage into thedifferential signals. Unfortunately, the offset voltage can degrade thenoise margin of the system. Since the offset voltage is generally aslowly varying signal, its frequency content is typically concentratednear DC. Further, the offset voltage varies with process, voltage, andtemperature (PVT) variations of the SERDES system.

SUMMARY

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used to limit the scope of the claimed subject matter.

The described embodiments provide a receiver having an input, an analogfront end, a first subtractor, and a slicer. The analog front end iscoupled to the receiver input and has an output. The first subtractorhas an output and has a first input coupled to the output of the analogfront end. The slicer has an output and has an input coupled to theoutput of the first subtractor.

In one embodiment, the receiver has a multiplier, a second subtractor,and an offset adaptation controller. The multiplier, has an output, afirst input coupled to the output of the slicer, and a second inputadapted to receive a weighting factor. The second subtractor, having anoutput, has a first input coupled to the output of the multiplier, and asecond input coupled to the input of the slicer. The offset adaptationcontroller has an input coupled to the output of the second subtractorand is configured to produce at an output a voltage coupled to a secondinput of the first subtractor.

In another embodiment, the receiver has a sampler and an offsetadaptation controller. The sampler has an input coupled to the output ofthe first subtractor, an output, and is configured to sample signalsapplied thereto at transitions in those signals. The offset adaptationcontroller has an input coupled to the output of the sampler and isconfigured to produce at an output a voltage coupled to a second inputof the first subtractor.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

Other aspects, features, and advantages of the present invention willbecome more fully apparent from the following detailed description, theappended claims, and the accompanying drawings in which like referencenumerals identify similar or identical elements.

FIG. 1 shows a high level block diagram of a SERDES communication systemaccording to exemplary embodiments of the invention;

FIG. 2 shows a high level block diagram of a SERDES receiver, similar tothat in FIG. 1, according to other embodiments of the invention; and

FIG. 3 illustrates an exemplary process for cancelling offset voltage inthe embodiments of FIGS. 1 and 2.

DETAILED DESCRIPTION

Table 1 summarizes a list of acronyms employed throughout thisspecification as an aid to understanding the described embodiments ofthe invention:

TABLE 1 ADC Analog to Digital AEQ Analog Equalizer Converter AFE AnalogFront End BER Bit Error Rate CDR Clock and Data Recovery DBE DigitalBack End DFE Decision Feedback DSP Digital Signal Processing EqualizerFFE Feed Forward Equalizer FIR Finite Impulse Response IC IntegratedCircuit ISI Intersymbol Interference NRZ Non-Return to Zero PAM PulseAmplitude Modulation PVT Process, Voltage, RF Radio FrequencyTemperature RX Receive SERDES Serializer - Deserializer SoC System onChip UI Unit Interval CTLE Continuous-Time Linear VGA Variable GainAmplifier Equalizer

Reference herein to “one embodiment” or “an embodiment” means that aparticular feature, structure, or characteristic described in connectionwith the embodiment can be included in at least one embodiment of theinvention. The appearances of the phrase “in one embodiment” in variousplaces in the specification are not necessarily all referring to thesame embodiment, nor are separate or alternative embodiments necessarilymutually exclusive of other embodiments. The same applies to the term“implementation”.

It should be understood that the steps of the exemplary methods setforth herein are not necessarily required to be performed in the orderdescribed, and the order of the steps of such methods should beunderstood to be merely exemplary. Likewise, additional steps might beincluded in such methods, and certain steps might be omitted orcombined, in methods consistent with various embodiments of the presentinvention.

Also for purposes of this description, the terms “couple”, “coupling”,“coupled”, “connect”, “connecting”, or “connected” refer to any mannerknown in the art or later developed in which energy is allowed to betransferred between two or more elements, and the interposition of oneor more additional elements is contemplated, although not required.Conversely, the terms “directly coupled”, “directly connected”, etc.,imply the absence of such additional elements. Signals and correspondingnodes or ports might be referred to by the same name and areinterchangeable for purposes here. The term “or” should be interpretedas inclusive unless stated otherwise.

Moreover, the terms “system,” “component,” “module,” “interface,”“model,” or the like are generally intended to refer to acomputer-related entity, either hardware, a combination of hardware andsoftware, software, or software in execution. For example, a componentmay be, but is not limited to being, a process running on a processor, aprocessor, an object, an executable, a thread of execution, a program,and/or a computer. By way of illustration, both an application runningon a controller and the controller can be a component. One or morecomponents may reside within a process and/or thread of execution and acomponent may be localized on one computer and/or distributed betweentwo or more computers.

Unless explicitly stated otherwise, each numerical value and rangeshould be interpreted as being approximate as if the word “about” or“approximately” preceded the value of the value or range. Signals andcorresponding nodes or ports might be referred to by the same name andare interchangeable for purposes here.

FIG. 1 shows a block diagram of an exemplary serializer-deserializer(SERDES) communication system 100 that might be implemented in anintegrated circuit. As shown in FIG. 1, SERDES system 100 includestransmitter 102, communication channel 104, and receiver 106. As shown,transmitter 102 might optionally include finite impulse response (FIR)filter 110 for conditioning data before transmission to communicationchannel 104. In some embodiments, the function of FIR 110 mightoptionally be moved from transmitter 102 to receiver 106 as receivedata. Transmitter 102 provides data u(n) as a transmit signal as serialdata symbols via communication channel 104, to receiver 106. Due to thechannel pulse response, h(t), of communication channel 104, thetransmitted signal bits, u(n), are received by receiver 106 as receivedata symbols, RX DATA x(t). Communication channel 104 might typically bea physical transmission medium, such as a backplane, drive head in amagnetic recording system, copper cables, or optical fibers.

Although described herein as being employed in a SERDES communicationsystem, described embodiments are not so limited, and some embodimentsmight be employed in alternative communications systems employing atransmitter and a receiver communicating over a communication channel.The communication channel might be at least one of fiber optics, one ormore coaxial cables, one or more twisted pair copper wires, and/or oneor more radio frequency (RF) channels. Additionally, various signalmodulation and de-modulation techniques might be employed. Further,although described herein as each “bit” of a signal having acorresponding logic value, it is understood that the various signalsdescribed herein might employ multi-bit data symbols based on variousdata encoding schemes, such as pulse amplitude modulation (e.g., PAM-4).Further, signal amplitudes might be expressed herein as −1 to 1 such asfor Non-Return to Zero (NRZ) signaling, although any signal encodingscheme might be employed.

After passing though communication channel 104, the analog transmitsignal is filtered or equalized by analog front end (AFE) 112 ofreceiver 106. As shown in more detail in FIG. 2, AFE 112 comprises aconventional variable gain amplifier (VGA) 114 to amplify the receivedsignal, and a continuous-time linear equalizer (CTLE) 116 coupled to theoutput of the VGA. An exemplary CTLE is described in U.S. patentapplication Ser. No. 13/244,985, titled “A Method of Compensating forNonlinearity in a DFE-based Receiver”, filed 26 Sep. 2011, attorneydocket number L11-0373US1, incorporated by reference herein in itsentirety.

The output of AFE 112 is provided to an analog summer 118, the purposeof which is described in more detail below, and the output of the summer118 is provided to an optional feed forward equalizer (FFE) 120,employed to reduce precursor ISI in the received data symbols. FFE 108applies equalization, in conjunction with a decision feedback equalizer(DFE) 136. The feedback signal from DFE 136, Θ(t), is subtracted fromthe filtered input signal z(t) by summer 126. DFE 136 is discussed inmore detail below. Consequently, analog summer 126 provides compensatedanalog signals, w(t), that are applied to a sampler 128 that is clockedby a data clock signal from clock data recovery block 130. As will beexplained in more detail below, the CDR 130 detects timing of the inputdata stream and uses such detected timing to set correct frequency andphase of two sampling clock signals, DATA CLOCK and TRANSITION CLOCK,based on the signals being received. The output samples y(k) from thesampler 128 are coupled to decision device (shown as data slicer 132)that, based on an input threshold, generates data decision bits v(k)corresponding to input symbols y(k). Data slicer 132 compares inputsamples in the analog domain to a threshold. Data slicer 122 mighttypically be implemented as a decision device based on an amplitudethreshold, but might also be a more complicated detector such as asequence detector. Data slicer 132 produces a binary version of w(k) ora quantized, multi-bit, value of w(k). Detected data v(k) is typicallybe provided to a utilization device (not shown), coupled to receiver106, for further processing.

In one embodiment, the data slicer 132 essentially quantizes the signalw(k) to a binary “1” or “0” based on the sampled analog value and aslicer threshold, s_(t). If the input to the slicer 132 at time k isy_(k), then the detected data bit output, v(k) of the slicer 132 isgiven as follows:

$\begin{matrix}{{v(k)} = {{{+ 1}( {{e.g.},{a\mspace{14mu} {{binary}\mspace{14mu} {''}}{1{''}}}} )\mspace{14mu} {if}\mspace{14mu} y_{k}} > {s_{t}\mspace{14mu} {and}}}} \\{= {{- 1}( {{e.g.},{a\mspace{14mu} {{binary}\mspace{14mu} {''}}{0{''}}}} )\mspace{14mu} {{otherwise}.}}}\end{matrix}$

In this example, the slicer 132 has a slicer threshold s_(t) of zero.

The DFE 136 is a conventional DFE and well known in the art. See, forexample, U.S. Patent Application Publication 2011/0274154, titled“Compensated Phase Detector for Generating One or More Clock SignalsUsing DFE Detected Data in a Receiver” by P. M. Aziz et al., filed 10May 2010, and incorporated by reference herein in its entirety, for oneexemplary embodiment of a DFE and the description thereof. In general,the DFE is a multi-tap filter having L taps that generates the feedbacksignal, Θ(t), constructed based on an estimate of inter-symbolinterference (ISI) present in input sample y(k). DFE 136 is employed toreduce post-cursor ISI in the received signal. DFE 132 generates thefeedback signal based on one or more previous data decisions of dataslicer 132 and one or more pulse response coefficients (taps)corresponding to the characteristics of the communication channel 104.The tap values are estimated and adapted by an adaption controller (notshown) based on error signal e(k) (not shown) generated from thedifference between a weighted data decision v(k) and the correspondingsampled input symbol y(k). It is noted that the DFE equalizer describedherein is well known and considered an analog implementation becausecompensation is done in the analog domain even though part of theequalizer might be implemented in digital form.

Exemplary operation of L-tap DFE 136 in FIG. 1 is as follows. A DFEcorrection signal, Θ(t), generated by a DFE filter 136 is subtracted byan analog summer 126 from the output, z(t), of the AFE 112 to produce aDFE corrected signal w(t), where w(t)=z(t)−Θ(t), Then the DFE-correctedsignal w(t) is then sampled by sampler 128 and quantized by slicer 132to produce the detected data bits v(k).

Because the output of slicer 132 (the detected data bits v(k)) is usedby filter 136 to produce the DFE output Θ(t), the filter 136 uses pastcorrected detected data to produce the DFE output Θ(t). For oneembodiment of the filter 136, the output of the DFE filter 136 is:

${\Theta (t)} = {\sum\limits_{i = 1}^{L}{{h(i)}{v( {- i} )}}}$

where h(i) represents the coefficients or weights of the L-tap DFEfilter 136 and

v(−i) represents past data decisions from the slicer 132. Furtherexplanation of the filter 136 and alternative embodiments thereof may befound in the above-mentioned U.S. Patent Application Publication2011/0274154. The value of the tap weights h(i) is determined during atraining period by analyzing an error signal, not shown, described inmore detail below in connection with FIG. 2. Generally and as wellunderstood in the art, the above-mentioned adaptation controller (notshown) coupled to the DFE 136 varies the tap weights using an exemplaryleast-mean-squared (LMS) algorithm to minimize the error signal.Alternatively, other iterative adaptation algorithms may be used.

The signal w(t) from the output of summer 126 is also sampled by sampler140 in response to the TRANSITION CLOCK from CDR 130 to produce samplesy(k−½). The transition sample data is denoted as y(k−½) to indicate issampled relative to y(k) by a phase offset of T/2, where T is the baudrate of the received symbols. The sampling at input symbol transitions,preferably after being quantized by slicer 142, advantageously allowsthe CDR 130 to better lock onto the phase of the incoming symbols.

The function of the CDR 130 is provide the clocks to the samplers 128and 140 so that when the input symbols are sampled by sampler 128 andpassed to slicer 132, the data is recovered properly despite the factthat the phase and frequency of the transmitted signal is not known. TheCDR 130 is often an adaptive feedback circuit and the feedback loop mustadjust the phase and frequency of the nominal clock to produce amodified recovered clock that can sample the analog waveform to allowproper data detection. In general, the CDR 130 is typically composed ofseveral components, such as a phase detector, a loop filter, and a clockgeneration circuit. The phase detector may be implemented as a bang-bangphase detector. For a general discussion of bang-bang phase detectors,see, for example, J. D. H. Alexander, “Clock Recovery from Random BinarySignals,” Electronics Letters, 541-42 (October, 1975), incorporated byreference herein in its entirety. For other implementations adaptablefor use as CDR 130, see “Method and Apparatus for Generating One or MoreClock Signals for a Decision-Feedback Equalizer Using DFE DetectedData”, by Aziz et al., U.S. Pat. No. 7,616,686, incorporated byreference herein in its entirety, and “Look-Ahead Digital Loop Filterfor Clock and Data Recovery”, by Aziz et al. U.S. Pat. No. 8,194,792,also incorporated by reference herein in its entirety.

Output from the sampler 140 is quantized by slicer 142 and the quantizeddata qy(k−½) is used by the above-described CDR 130 and an offsetadaptation block 150. As will be explained in more detail below, theoffset adaptation block 150 generates an offset correction voltage orsample o(k), using an adaptation loop process, that is applied to thenegative input of summer 118. The summer 118 subtracts the offsetcorrection voltage o(k) from the symbols passed by the AFE 112 to atleast partially cancel any offset voltage in the symbols w(t) beforethey are sampled by the sampler 128.

FIG. 2 illustrates another embodiment of the invention. Receiver 206 issimilar to receiver 106 of FIG. 1 except that instead of offsetadaptation based on the transition sample data y(k−½) in FIG. 1, anerror signal representing the difference between the DFE-correctedsignal y(k) and detected data bits v(k) from slicer 132, weighted with achannel estimate h₀, is used by offset adaptation block 150. Operationof the various blocks in FIG. 2 is substantially the same as describedabove for identically numbered blocks in FIG. 1.

A clock and data recovery unit (not shown), similar to CDR 130 in FIG.1, generates the clock signals necessary for receiver 206 to operate.

As mentioned above in connection with FIG. 1, an adaptation controller,here a conventional DFE and h₀ adaptation controller 232, adjusts thevalue of the tap weights h(i) determined during a training period byanalyzing a quantized error signal qe(k). Generally and as wellunderstood in the art, the DFE and h₀ adaptation controller 232 coupledto the DFE 136 varies the tap weight values thereof using an exemplaryleast-mean-squared (LMS) algorithm to minimize the error signal.Alternatively, other iterative adaptation algorithms may be used.

As in FIG. 1, data decisions v(k) are provided to DFE 132, whichgenerates a feedback signal, z(k), constructed based on an estimate ofinter-symbol interference (ISI) present in input sample y(k). DFE 132,using a tapped filter with coefficients determined by DFE and h₀adaptation controller 232 generates equalized output based on one ormore previous data decisions of data slicer 132. The tap coefficientscorrespond to one or more pulse response coefficients of thecommunication channel 104. The DFE and h₀ controller 232 adapts based ona quantized version of an error signal e(k) generated from thedifference between a weighted data decision v(k) and the correspondinginput sample y(k). Weighting coefficient h₀ from the controller 232 isbased on an estimate of the first coefficient of the transfer functionof channel 104. For purposes here, h₀ is proportional to the amplitudeof the received signals from the channel 104. The weighted datadecisions are generated by multiplier 234, and error signal e(k) isgenerated as the difference between the weighted decision h₀v(k) and theinput sample y(k) by subtractor 236. The error signal e(k) might also beemployed by the above-described CDR circuitry (not shown) for timingrecovery. The error signal e(k) is quantized by slicer 238 to producequantized error signal qe(k) that is applied to DFE adaptationcontroller 232 to update and adapt parameters of the various filters(coefficients and taps) of AFE 112, FFE 120 if present, and DFE 132. Theslicer 238 operates substantially the same as slicer 132 and hasapproximately the same threshold voltage.

Offset adaptation block 150 receives the quantized error signal qe(k) todetermine the offset o(k) applied to subtractor 118. Alternatively, whenthe offset adaptation block 150 and DFE adaptation block 232 areimplemented in analog form, the offset adaptation block 150 receives theerror signal e(k) instead of the quantized version. In anotherembodiment, the offset adaptation block 150 is implemented in or by theDFE and h₀ adaptation controller 232. However, the offset adaptationadaption process described below can be implemented independently of theDFE adaptation processes undertaken by the controller 232.

As shown in FIGS. 1 and 2, the receiver 106, 206 consists of analogfront-end (AFE) that typically consists of analog circuits such as VGA114 and CTLE 116 which respectively amplify and equalize the signalinput to the receiver. These circuits might introduce unknown andrelatively slowly varying offset into the signal it process which causesthe AFE output to shift up or down based on the polarity of the AFEoffset voltage. There might be other sources that result in voltageoffset as seen by the slicer 132, such as the transmitter 102 and thechannel 104.

For purposes of this description, the input signals and signals z(t),w(t), θ(t), and y(k) are bipolar signals, e.g., ranging between +1 and−1. Similarly, the recovered data bits v(k) have values of +1 and −1depending on the value of the signal applied to slicer 132. However,other values may be used with a suitable adjustment to the offsetcorrection technique described below.

In the offset correction technique implemented in offset adaptationblock 150 in FIG. 1, either the transition samples y(k−½) or thequantized version of transition samples qy(k−½) is used to calculate theAFE offset voltage o(k). Alternatively and as shown in FIG. 2, eitherthe error signal e(k) or the quantized (sliced) error signal qe(k) isused to calculate the AFE offset voltage. In both embodiments, thecalculated offset voltage o(k) is subtracted from the AFE output signalto remove the effect of AFE offset voltage. In these embodiments, theoffset voltage introduced by AFE 112 is adapted using transition orerror samples according to minimum mean squared error (MMSE) criterion.The value of o(k) is computed as o(k)=o(k−1)+μg(k−1), where g(k−1) is agradient with respect to the immediately preceding offset voltage o(k−1)according to the MMSE criteria and μ is a step size.

According to the MMSE criteria for the receiver 106 in FIG. 1, g(k−1) isgiven as either −y(k−½) or qy(k−½) depending on the implementation ofthe receiver 106 in FIG. 1. Then the update equation of o(k) is given aseither o(k)=o(k)+μy(k−½) or o(k)=o(k)+μqy(k−½). The average value ofeither bipolar symbols qy(k−½) or analog samples y(k−½) gives thedirection/sign of the AFE offset voltage and the step size μ determinesquantization level of corrected AFE offset voltage.

For the receiver 206 in FIG. 2, in one embodiment, the value of o(k) isalso computed as o(k)=o(k−1)+μg(k−1), where g(k−1) is a gradient withrespect to the immediately preceding offset voltage o(k−1) according tothe MMSE criteria and μ is a step size. According to the MMSE criteriafor the receiver 206 in FIG. 2, g(k−1) is given as either −e(k) or−qe(k) depending on the implementation of the receiver 206. Then theupdate equation of o(k) is given as either o(k)=o(k)+μe(k) oro(k)=o(k)+μqe(k). The average value of either bipolar symbols qe(k) oranalog samples e(k) gives the direction/sign of the AFE offset voltageand the step size μ determines quantization level of corrected AFEoffset voltage. The step size μ is dependent on the amount of offsetrange and number of intervals or steps the range is to be divided into.For example, if the offset ranges from −60 mV to +60 mV and the numberof steps is 32, then μ is 120 my/32 or 3.75 mV/step or 3.75 10⁻³ V/step.The offset range and number of steps needed is system dependent but theexpected range of μ is typically between 10⁻⁶ and 10⁻² V/step.

For both embodiments, the AFE offset voltage o(k) is based on digitaladaptation process using either transition samples or error samples toremove the impact of AFE offset voltage on the system 100.

FIG. 3 illustrates one embodiment of a digital adaptation process 300 togenerate the offset voltage sample o(k). After an input signal isapplied to the receiver in step 302, the offset sample o(k) and avariable representing a previous offset sample, o(k−1), are initializedto zero or some other known value. Then in step 306 the offset setvoltage sample o(k) is applied to the summer 118 to begin canceling anyDC offset from the AFE 112 and any other analog circuitry the AFEcouples to. After sufficient time for the system to adapt to the changein offset voltage in step 308, the gradient g(k−1) is read (here g(k−1)is either y(k−½) or qy(k−½) for the embodiment in FIG. 1 or is either−e(k) or −qe(k) for the embodiment in FIG. 2) in step 310. If theadaption process is to terminate because, for example, the gradient isless than a threshold value or enough time or adaptation cycles hasoccurred, the process ends with step 312. However, if the adaptation isto continue, then in step 314 the next offset voltage o(k) is calculatedas described above and control passes back to step 306 for anothercycle.

While embodiments have been described with respect to circuit functions,the embodiments of the present invention are not so limited. Possibleimplementations, either as a stand-alone SERDES or as a SERDES embeddedwith other circuit functions, may be embodied in a single integratedcircuit, a multi-chip module, a single card, system-on-a-chip, or amulti-card circuit pack. As would be apparent to one skilled in the art,the various embodiments might also be implemented as part of a largersystem. Such embodiments might be employed in conjunction with, forexample, a digital signal processor, microcontroller, field-programmablegate array, application-specific integrated circuit, or general-purposecomputer. As would be apparent to one skilled in the art, variousfunctions of circuit elements might also be implemented as processingblocks in a software program. Such software might be employed in, forexample, a digital signal processor, microcontroller, or general-purposecomputer. Such software might be embodied in the form of program codeembodied in tangible media, such as magnetic recording media, opticalrecording media, solid state memory, floppy diskettes, CD-ROMs, harddrives, or any other non-transitory machine-readable storage medium,wherein, when the program code is loaded into and executed by a machine,such as a computer, the machine becomes an apparatus for practicing theinvention. When implemented on a general-purpose processor, the programcode segments combine with the processor to provide a unique device thatoperates analogously to specific logic circuits. Described embodimentsmight also be manifest in the form of a bitstream or other sequence ofsignal values electrically or optically transmitted through a medium,stored magnetic-field variations in a magnetic recording medium, etc.generated using a method and/or an apparatus as described herein.

It should be understood that the steps of the exemplary methods setforth herein are not necessarily required to be performed in the orderdescribed, and the order of the steps of such methods should beunderstood to be merely exemplary. Likewise, additional steps might beincluded in such methods, and certain steps might be omitted orcombined, in methods consistent with various embodiments.

It is understood that embodiments of the invention are not limited tothe described embodiments, and that various other embodiments within thescope of the following claims will be apparent to those skilled in theart.

1. A receiver having an input, the receiver comprising: an analog frontend coupled to the receiver input and having an output; a firstsubtractor having a first input coupled to the output of the analogfront end and having an output; a slicer coupled to the output of thefirst subtractor and having an output; a multiplier having an output, afirst input coupled to the output of the slicer; and a second inputadapted to receive a weighting factor; a second subtractor having anoutput, a first input coupled to the output of the multiplier, and asecond input, coupled to the input of the slicer; and an offsetadaptation controller having an input coupled to the output of thesecond subtractor and configured to produce at an output a signalcoupled to a second input of the first subtractor.
 2. The receiver ofclaim 1 further comprising a sampler disposed between the output of thesecond subtractor and the input of the slicer.
 3. The receiver of claim1 wherein the weighting factor is a signal proportional to an amplitudeof signals applied to the input of the receiver.
 4. The receiver ofclaim 1 further comprising another slicer disposed between the output ofthe second subtractor and the input of the offset adaptation controller.5. The receiver of claim 1 further comprising: a third subtractor havinga first input coupled to the output of the first subtractor, a scoopinput, and an output; and a decision feedback equalizer having an outputand at least one tap coefficient and coupled to the output of theslicer; wherein the output of the decision feedback equalizer is coupledto the second input of the third subtractor.
 6. The receiver of claim 5further comprising a feed-forward equalizer disposed between the outputof the first subtractor and the first input of the third subtractor. 7.The receiver of claim 6 further comprising: a decision feedbackequalizer adaptation controller coupled to the output of the slicer andthe output of the second subtractor; wherein the decision feedbackequalizer adaptation controller generates the weighting factor andcontrols the decision feedback equalizer, the feed-forward equalizer,and the analog front end.
 8. The receiver of claim 7 wherein thedecision feedback equalizer adaptation controller and the offsetadaptation controller are one controller.
 9. The receiver of claimwherein the offset adaptation controller is configured to perform thefollowing steps: read the input of the offset adaptation controller togenerate a gradient; calculate a offset value based on a past offsetvalue adjusted by a combination of the gradient and a step size; andoutput to the output of the offset adaptation controller the calculatedoffset value.
 10. The receiver of claim 9 wherein the steps arerepeated.
 11. The receiver of claim 9 wherein the analog front end has aDC offset and the step size is substantially determined by a range ofthe DC offset divided by a desired number of steps.
 12. The receiver ofclaim 11 wherein the step size ranges from approximately 10⁻⁶ toapproximately 10⁻² V/step.
 13. The receiver of claim 1 wherein thereceiver is implemented in an integrated circuit. 14.-26. (canceled) 27.In a system including a receiver, the receiver having an input and ananalog front end coupled to the input, a method comprising: applying aninput signal to the receiver input, the input signal having an amplitudelevel; filtering the applied input signal with analog front-endcircuitry; subtracting from the filtered input signal an offsetcancelation value to form a compensated signal; slicing the compensatedsignal; generating an error signal based on the sliced compensatedsignal and a weighting factor; and calculating the offset cancelationvalue based sari a past offset cancelation value adjusted by acombination of the error signal and a step size; wherein the weightingfactor is proportional to the amplitude level.
 28. The method of claim27 further comprising the step of: slicing the error signal; wherein thestep of calculating the offset cancelation value is adjusted based onthe sliced error signal. 29.-32. (canceled)
 33. The method of claim 27wherein the step of generating an error signal based on the slicedcompensated signal and a weighting factor comprises the step of:multiplying the sliced compensated signal by the weighting factor.